1. Field of the Invention
The present invention relates to a semiconductor device including a semiconductor chip mounted on a wiring substrate and a method of manufacturing the same.
Priority is claimed on Japanese Patent Application No. 2008-166390, filed Jun. 25, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
Conventionally, a BGA (Ball Grid Array)-type semiconductor device includes: a wiring substrate, on a top surface of which multiple connection pads are provided, and a bottom surface of which multiple lands are provided to be electrically connected to the connection pads; a semiconductor chip provided on the top surface of the wiring substrate; wires electrically connecting electrode pads provided on the semiconductor chip and the connection pads provided on the wiring substrate; a seal which is made of insulating resin and covers at least the semiconductor chip and the wires; and external terminals provided on the lands.
However, there has been a problem of warpage of a semiconductor device due to the difference in values of thermal expansion coefficients between a wiring substrate and a seal resin. Consequently, solder balls are not correctly connected upon a secondary mounting of the semiconductor device onto a motherboard.
Additionally, a BGA-type semiconductor device to be used for a PoP (Package on Package) cannot be electrically connected to another semiconductor device to be stacked when the semiconductor device and the other semiconductor device warp in the opposite directions.
Further, the difference in values of thermal expansion coefficients between the wiring substrate and the semiconductor chip causes stress to be applied onto a periphery of the semiconductor chip, and especially onto four corners thereof. Thereby, solder balls provided under the four corners crack, degrading the reliability of secondary mounting of the semiconductor device.
Such a semiconductor device is manufactured using MAP (Mold Array Process) and includes multiple wiring substrates and a seal collectively covering the substrates, causing the problem of warpage.
For example, Japanese Patent, Laid-Open Publication Nos. 2006-269861, 2007-66932, and 2006-286829 are related art for preventing warpage of a semiconductor device.
Japanese Patent, Laid-Open Publication Nos. 2006-269861 and 2007-66932 disclose a semiconductor device including a lower substrate (wiring substrate), semiconductor chips provided above the lower substrate, a seal covering the semiconductor chips, and an upper board provided over the seal and the semiconductor chips. A thermal expansion coefficient of the upper board is substantially the same as that of the lower substrate.
Japanese Patent, Laid-Open Publication No. 2006-286829 discloses a semiconductor device including a first resin that covers a semiconductor chip mounted on a wiring substrate and prevents deformation of bonding wires or corrosion of connections between the semiconductor chip and the bonding wires, and a second resin (seal) that is provided over the wiring substrate and the first resin to prevent warpage of the wiring substrate.
In any of the related art, the upper board or the resin layer having substantially the same thermal expansion coefficient as that of the wiring substrate is provided over the seal covering the semiconductor chip mounted on the wiring substrate, thereby preventing warpage of the semiconductor device caused by the difference in values of thermal expansion coefficients between the wiring substrate and the seal.
However, any of the related art are silent about warpage of the semiconductor device and stress applied to the four corner of the semiconductor device which are caused by the difference in values of thermal expansion coefficients between the wiring substrate and the semiconductor chip. Therefore, solder balls provided around a periphery of the semiconductor chip, especially around the four corners thereof crack.
Additionally, the upper board or the resin layer for preventing warpage is provided over the seal covering the semiconductor chip, resulting in variation in thickness of the seal. Thereby, the semiconductor chip might be warped due to the variation.
Warpage of one semiconductor device causes a more significant problem of warpage of multiple stacked semiconductor devices having the PoP structure. Additionally, the problem is more significant as the size of the wiring substrate increases.